One time programmable (OTP) and multi-time programmable (MTP) memories have been recently introduced for beneficial use in a number of applications where customization is required for both digital and analog designs. These applications include data encryption, reference trimming, manufacturing ID, security ID, and many other applications. Incorporating OTP and MTP memories nonetheless typically comes at the expense of some additional processing steps.
An NMOS OTP implementation is disclosed by U.S. Pat. No. 6,920,067, incorporated by reference herein. The device in this reference is programmed with channel hot-hole-injection. The disclosure teaches that the device is programmed into conducting state, after the channel hot hole injection. However, it is unclear whether the device actually works in the way the inventors claim. That is, it is not apparent that the channel current will be initiated to induce hot-hole-injection since the state of the floating gate is unknown and there is no available means to couple a voltage unto the floating gate. An NMOS device will conduct a channel current to initiate the hot hole injection only when the floating gate potential is sufficient to turn on the device, or when the threshold voltage is always low initially to allow channel current conduction. The only way to ensure either scenario is to introduce an additional process step to modify the turn on characteristics of the NMOS. Now assuming the channel is conducting initially and hot holes are injected, the holes injected on the floating gate will make the device more conductive. So the device basically goes from a conductive state (in order to initiate channel current for hot hole injection) to a highly conductive state. This is not a very optimal behavior for a memory device.
Another prior art device described in U.S. Pat. No. 7,939,861 (incorporated by reference herein) shows a slightly different approach to the problem of providing a programming voltage to a floating gate embodiment of an OTP device. In this design, shown in FIG. 4, the drain border length L1 is increased relative to the source side length L1 to increase a coupling ratio to the eraseable floating gate 416. By increasing the coupling ratio, the amount of channel current is increased; therefore the charge injection into the floating gate will also increase. The drawbacks of this cell, however, include the fact that the cell and channel 412 must be asymmetric, and the coupling is only controlled using the length dimension of the active regions. Because of these limitations, it also does not appear to be extendable to a multi-level architecture. Moreover, it apparently is only implemented as a p-channel device.
Accordingly there is clearly a long-felt need for a floating gate type programmable memory which is capable of addressing these deficiencies in the prior art.